There is a general desire for continually smaller size for computing and electronic devices and components, even as higher performance and storage capacity is expected from the devices. Such desire is especially true for memory circuits or memory devices. It will be understood that the more discrete circuit components and the greater the real estate used, the more the devices consume power. Size and power consumption are significant factors in electronics and memory devices, especially for handheld and mobile applications. Recent developments in device manufacturing offer three dimensional (3D) circuit structures to create electronic devices that have higher densities.
However, the physics of various materials and processing techniques introduce performance limitations on resulting high density devices that restrict the commercial viability of such devices. One technique developed with 3D circuit devices is the use of a conductive channel to conduct a current to enable active operation of stacked circuit elements. However, traditional processing has resulted in undesirable effects when electrically connecting a source layer to the channel. Traditional sources have either provided a good reservoir for charge carriers to move into the channel (sources with good GIDL (gate induced drain leakage)) but with high resistance, or sources that have lower GIDL and low resistance. Low resistance sources have traditionally acted as carrier sinks, rather than providing a good source to the channel conductor.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.